Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
Read operations usually are performed on floating gate memory cells using sense amplifiers. A sense amplifier for this purpose is disclosed in U.S. Pat. No. 5,386,158 (the “'158 Patent”), which is incorporated herein by reference for all purposes. The '158 Patent discloses using a reference cell that draws a known amount of current. The '158 Patent relies upon a current mirror to mirror the current drawn by the reference cell, and another current mirror to mirror the current drawn by the selected memory cell. The current in each current mirror is then compared, and the value stored in the memory cell (e.g., 0 or 1) can be determined based on which current is greater.
Another sense amplifier is disclosed in U.S. Pat. No. 5,910,914 (the “'914 Patent”), which is incorporated herein by reference for all purposes. The '914 Patent discloses a sense circuit for a multi-level floating gate memory cell, which can store more than one bit of data. It discloses the use of multiple reference cells that are utilized to determine the value stored in the memory cell (e.g., 00, 01, 10, or 11). Current mirrors are utilized in this approach as well.
An alternative to using reference cells is to use a reference current. The reference current is used to determine the value stored in the memory cell. This is a known technique in the prior art. However, one drawback of this approach is that if the same reference circuit is used for each memory cell within a semiconductor die, the temperature variations within the die during normal operation or variations during processing will cause the reference currents to vary throughout the die.
What is needed is an improved sensing circuit that utilizes a current reference signal, where the signal can be adjusted to account for temperature variations and process variations that occur within a semiconductor die.